1. Technical Field
The present invention relates to a semiconductor device and a method for manufacturing the same.
2. Related Art
Recently, a copper (Cu) interconnect having low resistance is usually being employed in an advanced semiconductor device pursuing down-scaling and high-speed operation. A copper interconnect is formed by a damascene process. In the damascene process, an interconnect is formed such that a concave portion is formed in an insulating interlayer, a barrier metal layer and a copper layer are formed in the concave portion to embed the concave portion, and portions of the copper layer and the barrier metal layer which are exposed outside the concave portion are removed by a chemical mechanical polishing (CMP) technique. A multi-layer interconnect structure is formed by repetitively performing this procedure.
Also, as a semiconductor device pursues a high performance, a low dielectric constant layer (so-called low-k layer) which is lower in relative dielectric constant (k value) than SiO2 is used as an insulating interlayer of a multi-layer interconnect structure. There are various kinds of low dielectric constant layers, but low dielectric constant layers are commonly poor in adhesion or mechanical strength. Therefore, there is a problem in that when a trench is formed in a low dielectric constant layer, an altered (degraded) layer is formed on a sidewall of the trench (concave portion) during an etching process or a resist ashing process, and thus an effective k value is increased, causing capacitance between interconnects to be increased.
Japanese Laid-open patent publication No. 2004-72080 discloses a method in which a concave portion is formed in a low dielectric constant layer using a photoresist layer, the photoresist layer is removed, the concave portion is embedded with a conductive layer, and then an altered (degraded) layer is removed. In this method, a dielectric constant layer is embedded on the whole surface of a void generated when the altered layer is removed and is then polished by a CMP process.
Japanese Laid-open patent publication No. 2007-5679 discloses a technology that a via hole is formed in a low dielectric constant layer using a resist layer (by photolithography process), the resist layer is removed, and a damage layer which is formed on a via hole sidewall through resist-removing process is finally removed. Thereafter, the whole surface of the via hole is embedded with a low dielectric constant organic material (such as polybenzoxazole and polyimide which does not have a Si—O bond and has high etching selectivity of equal to or more than 30 to the low dielectric constant layer), and a resist layer is formed thereon to form a trench. The resist layer and the low dielectric constant organic material in the via hole are removed when the trench is formed.
WO 2004/107434 discloses a structure that an insulating barrier layer containing an organic material is formed between an insulating interlayer and a metal interconnect.